Parallel-in shift register mux’d with uC

The parallel-in shift register is one of many ICs that can be used to multiplex one side of the matrix we are scanning. The basic concept is to save microcontroller pins by multiplexing the rows of your matrix. So, rather than just having the microcontroller read in a row in parallel, data is clocked in through a shift register. In this way, a very large number of rows can be addressed with only 3 microcontroller pins. An example of this is shown below.

shift register mux schematic

Figure 1 – Example parallel-in shift register mux schematic.

he 74HC165 is a parallel-in, serial-out shift register. There are other chips with similar functionality, but this one is the most common. It has a parallel load pin (PL), which stores the data present at the input pins when it goes high. the data is then clocked out with every low to high transition on the clock pin (CP). A series of these chips can be placed into a long line, and they can pass data down the line until it all reaches the microcontroller.

Of the 3 partially mux’d matrix options (parallel-in, parallel-out, and 3 to 8), the parallel-in is a close third behind the 3 to 8 method. It’s the slowest option, as all 8 bits need to be serially clocked in for every column. The SPI interface can be used to speed up this process, or have it happen in the background, but then you’re tying up your SPI peripheral. It also is incapable of allowing switches to trigger external interrupts, as none of them are tied directly to the microcontroller.

To its credit, it consumes a similar amount of microcontroller lines (3 compared to parallel-out’s 2), and can scale to many more switches using only those 3 lines. the 3 to 8 method requires an additional pin for each additional bank of 8 columns. But, it also requires pull-up resistors on the ’165, adding to part cost. This method is only recommended if you happen to have ’165′s you need to use up, or your SPI peripheral is free.