3 to 8 decoder mux’d with shift register

This is a similar approach to the dual shift register mux, except the column is activated with a 3 to 8 decoder instead of a shift register. It has the advantage of being a bit faster, but at the expense of 2 more pins. A schematic representation is shown below.

3 to 8 and shift register mux

Figure 1 – Example 3 to 8 decoder and shift register mux schematic.

The columns are first addressed by the 3 to 8 decoder, and then the parallel-in shift register is latched and its data clocked in. It has the same disadvantages of all the parallel-in shift register options: Slow data input unless you use your SPI peripheral, the inability to use external interrupts, and the necessity of external pull-up resistors. Since it consumes 6 microcontroller pins and requires 2 ICs, its a more expensive and slower option in comparison to the parallel-out shift register mux. It is mostly included here for completeness.